The DAC module is based on the multi-level delta-sigma Asahi Kasei Microdevices AK4490 IC in a "dual mono" mode. Each channel uses a separate independent DAC IC together with antialiasing filters and power supplies. The synthesis of control signals, the interface module synchronization signal, the preliminary processing and the data stream separation are carried out in a high-speed 4th generation CPLD. To increase noise immunity, all control, data and synchronization lines are equipped with receiving buffer elements. The DAC module digital functional notes are powered by individual integral regulators, with individual LC filters for each group of logic elements.
The dual frequency masterclock oscillator is specially designed and implemented to ensure ultra low phase noise (jitter). It is a super high short-term stability special crystal cut quartz oscillator with a very high Q Factor powered through a symmetric RF filter from a low noise discrete regulator.
The DAC IC’s analog output signals are precisely filtered by individual antialiasing Bessel 3½ order filters and processed by 2-stage filters-subtractors to achieve maximum in-phase noise reduction. Every analogue processing stage utilizes extremely linear and wideband Op Amps. The outputs are buffered by discrete class A single-ended followers. Each DAC IC is powered by 4 independent ultra low noise discrete regulators with very high long term and temperature stability. The ratio of the DAC IC’s reference voltages and power supply voltages is selected by the criteria of minimizing the THD level and ensuring the uniformly falling distortion spectrum envelope.
DAC module analogue stage passive circuits utilize the precision low-noise metal film resistors and precision foil capacitors. The power supply rectifier filter circuits utilize low-impedance and high ripple current electrolytic capacitors. All the analogue circuits are powered by separate low noise discrete voltage regulators with high ripple suppression and aperiodic transient response.